Implantable N-phasic defibrillator output bridge circuit

ABSTRACT

An output bridge circuit comprising four independently controlled transistors connected between first and second electrode terminals and a defibrillation capacitor. Two of the four transistors are driven by push-pull driver circuits and connected between the capacitor and the first and second electrode terminals. The remaining two transistors are connected between the first and second electrode terminals and ground terminals. By triggering one of the transistors connected to the push-pull driver circuits and one of the transistors connected between the electrode terminals and the ground terminal, a mono-phasic, multi-phasic, or sequential defibrillation pulse can be generated by activating the appropriate transistors.

BACKGROUND OF THE INVENTION

The present invention relates to an implantable defibrillator outputcircuit, and more specifically to an output bridge circuit for issuingmono-phasic, multi-phasic, and sequential defibrillation pulses.

In the field of implantable defibrillators, it has been found that abi-phasic defibrillation pulse applied to a fibrillating heart is usefulin controlling and arresting ventricular fibrillation. See for example,commonly assigned U.S. patent application Ser. No. 143,061, filed Jan.12, 1988, and entitled BI-PHASIC PULSE GENERATOR FOR AN IMPLANTABLEDEFIBRILLATOR. This application discloses a circuit for generating abi-phasic voltage pulse, the circuit including first and secondthyristors for regulating the voltage of a capacitor. The circuitfurther includes an output sensing section for sensing the exponentialdecay of the capacitor and signalling a control circuit to switch metaloxide silicon insulated gate transistors (MOSIGT) in a ground circuitsuch that after one thyristor applies a voltage pulse to the heart in afirst polarity the control circuit interrupts to turn off the thyristor.The other thyristor then applies the voltage pulse to the heart in asecond and opposite polarity. It, in turn, is turned off by a secondMOSIGT. While this disclosed circuit is capable of generating abi-phasic defibrillation pulse, the ground return terminal needs to bedisconnected in order to commutate the current flow through theelectrodes to the heart.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to provide animplantable defibrillator output circuit capable of delivering amulti-phasic defibrillation pulse without having to repeatedlydisconnect the ground return reference terminal.

It is another object of this invention to provide an implantabledefibrillator output bridge circuit wherein energy on a defibrillatorcapacitor can be used for the delivery of bi-phasic, tri-phasic, andsequential defibrillation pulses.

The present invention comprises an implantable defibrillator outputcircuit comprising a bridge configuration having four Metal OxideSilicon Insulated Gate Transistors (MOSIGT's) and arranged with the toptwo transistors having transformer isolated gate drives and the bottomtwo transistors having turn off time control and low impedance clamping.Furthermore, all four MOSIGT's have independent on/off control to allowfor mono-phasic, bi-phasic, tri-phasic, and sequential defibrillationpulses, and permit the selection of delivery polarity as either positiveor negative without having to disconnect the ground return reference.

The above and other objects and advantages will become more readilyapparent when reference is made to the following description taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic diagram of the implanatabledefibrillator output bridge circuit in accordance with the presentinvention.

FIG. 2 is a schematic diagram illustrating the use of the implantabledefibrillator output bridge circuit of the present invention inconjunction with an implanatable defibrillation system.

FIGS. 3a-3h are graphical plots of defibrillation pulses produced by theoutput bridge circuit illustrated in FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring first to FIG. 1, the implantable defibrillator output bridgecircuit is generally shown at 10. The circuit 10 comprises a leftportion 12a and a right portion 12b. With the exception of thetransistor Q23 and resistor R11, the circuit portions 12a and 12b aremirror images of each other. Therefore, a detailed description ofcircuit portion 12a will be made first and a brief description ofcircuit portion 12b will follow.

The circuit 10 includes input signal pins P1A, P2A, P3A, P4A, P5A, P3B,P4B, P3C, and P4C. In addition, output pins are provided at patch+andpatch-for connecting the circuit 10 to defibrillation electrodesimplanted on the heart. Ground return pins are also provided for eachside of the circuit 10, the function of which will be describedhereinafter. Each circuit portion 12a and 12b connects to a capacitor C3at respective pins designated Vcap. The four MOSIGT's are transistorsQ1, Q2, Q12, and Q13. The top transistors Q1 and Q12 have transformerisolated gate drives. The bottom transistors Q2 and Q13 have controlledturn off time and low impedance clamping. Each MOSIGT Q1, Q2, Q12, andQ13 has independent on/off control. As will become more apparenthereinafter, transistors Q1 and Q12 are used for controlling themulti-phasic nature of the defibrillation pulse, while transistors Q2and Q13 set the polarity of the defibrillation pulse by selecting one ofthe pins patch+or patch-as the ground-return.

Input signal pin P1A connects to push-pull driver transistorconfiguration comprising transistors Q3, Q4, Q5, and Q6. The push-pulldriver generates a square wave with amplitude +/-Gate-bias. Thepush-pull driver is connected to a DC blocking capacitor C1, which inturn is connected to the primary side of the pulse transformer T1. Thegate and source of the transistor Q7 connects across the secondary sideof the transformer T1 while the gate and drain of Q7 are connected inparallel with resistor R1 and zener diode Z1. The gate and source of thetransistor Q1 are connected in parallel with resistor R1 and zener diodeZ1. Diode D1 connects across the drain and source of the transistor Q1.

Diodes D3 and D4 connect the source of transistor Q1 to the drain oftransistor Q2. Diode D2 connects across the source and drain of thetransistor Q2. The gate of the transistor Q2 is connected to resistor R5and the emitters of the transistors Q9 and Q10. Resistor R5 alsoconnects to the drain of the transistor Q11. Connected across the gateand source of transistor Q11 is resistor R6.

A series connection of resistor R3 and diode D9 is connected to the baseof the transistor Q9. Similarly, the series connection of resistor R4and diode D10 is connected to the base of the transistor Q10. Inputsignal pins P4A and P4B connect between resistor R3 and diode D9, andresistor R4 and diode D10, respectively. Transistors Q23 is providedwith resistor R11 connected across its gate and source for providingaccess to an external dump load as will be explained hereinafter.

The circuit portion 12b is the same as circuit portion 12a with theexception of transistor Q23 and resistor R11. Transistors Q14, Q15, Q16,and Q17 comprise a push-pull driver configuration connected to the pulsetransformer T2 in the same way as transistors Q3-Q6. Transistor Q18 isconnected to the secondary side of the transformer T2 and to resistorR2, zener diode Z2, and transistor Q12, similar to the connectionsbetween transistor Q7, resistor R1, zener diode Z1 and transistor Q1 incircuit portion 12a.

Diodes D7 and D8 connect the transistor Q1 to the transistor Q13 in asimilar manner as diodes D3 and D4 connect transistor Q1 to transistorQ2. The gate of transistor Q13 connects to the emitters of transistorsQ20 and Q21 and to resistor R9. The series connection of resistor R7 anddiode D11 is connected to the base of the transistor Q20. Similarly, theseries connection of diode D12 and resistor R8 is connected to the baseof transistor Q21. The input signal control pins P3A and P3B connectbetween resistor R7 and diode D11, and resistor R8 and diode D12,respectively. Resistor R9 connects the emitters of the transistors Q20and Q21 to the drain of the transistor Q22. Resistor R10 is connectedacross the gate and source of transistor Q22.

The operation of circuit 10 will now be described with respect to thetransistor Q1 and Q13 corresponding to input signal pins P1A, and P3A,P3B, and P3C, respectively, while pins P4A, P4B, P2A and P4C are atground potential. The Gate-bias voltage is positive with respect toground-return. To operate transistor Q1, a positive going pulse withrespect to the ground-return is applied to pin P1A. This drives thepush-pull driver configuration of transistors Q3-Q6 to generate a squarewave with amplitude +/-Gate-bias. This drives the primary side of thepulse transformer T1 via the DC blocking capacitor C1. A positive pulseon the dotted secondary of the pulse transformer T1 causes the intrinsicbody diode, created by making the gate more negative than the source, toconduct, which then causes the gate of transistor Q1 to chargeto+Gate-bias volts, turning transistor Q1 on. As long as a positivevoltage pulse is applied on pin P1A, transistor Q1 is on until the gatecharge is depleted. A negative pulse on the secondary of pulsetransformer T1 caused by pin P1A returning to ground potential forcesthe gate of the transistor Q7 to be more positive than the source oftransistor Q7, so that transistor Q7 turns on providing a low impedancedischarge path for the gate charge on transistor Q1. Hence, Q1 turnsoff. The zener diode Z1, when forward biased, prevents the gate oftransistors Q1 from charging to -Gate-bias volts. The overall impedancethat the gate of transistor Q1 sees when charging or discharging is theoutput impedance of the push-pull driver configuration of transistorsQ3-Q6. Resistor R1 provides a high impedance gate discharge path, gateto source, of transistor Q1, that prevents charge from accumulating onthe gate of transistor Q1 and therefore prevents false turn on. Thezener diode Z1 clamps positive gate to source voltage of transistor Q1in excess of positive gate-bias that may be caused via the transfercapacitance of transistor Q1 by rapidly changing positive drain tosource voltages. Zener diode Z1 also clamps negative gate to sourcevoltages in excess of a diode drop caused by the same conditions.Further, zener diode Z1 protects the gate to source potential oftransistor Q1 from exceeding its maximum ratings and also helps tominimize false turn on caused by a change of voltage with respect totime seen by the drain to source of transistor Q1.

Diode D1 protects Q1 if the source potential is greater than drainpotential. Diode D3 also protects Q1 in an effort to keep current fromflowing into the source of Q1 if the cathode side of diode D3 becomesmore positive than the drain of transistor Q1. This condition can occurdue to the stray inductance and the counter EMF generated by the changein current with respect to time when the other side of the bridge isturned off. Diodes D6 and D8 protect transistor Q13 in the same way asdiodes D1 and D3 protect transistor Q1.

To operate transistor Q13, input signal pins P3A, P3B, and P3C areemployed. A positive going pulse with respect to ground-return on pinsP3A and P3B turns on transistor Q20, and turns off transistor Q21,respectively, which then allows the gate of transistor Q13 to chargeto+Gate-bias volts, thus turning transistor Q13 on. The input signal atpin P3C must be kept low to keep transistor Q13 on. When pin P3A is setlow, Q20 is turned off. P3C is set high while P3B is still high to turnon transistor Q22. Thus, the gate of transistor Q13 slowly dischargesthrough resistor R9. By allowing the gate to slowly discharge, the draincurrent through transistor Q13 slowly decreases thereby reducing thechange with respect to time of the drain current. The input signal atpin P3B was positive and returns to ground-return. This turns ontransistor Q21 to provide a low impedance clamp to the gate oftransistor Q13, thus turning transistor Q13 off. Once pin P3B is setlow, P3C can be set low. A low impedance clamp is required to preventtransistor Q13 from falsely turning on due to induced gate voltagescaused by rapidly changing positive drain to source voltages that couplethrough the transfer capacitor. Resistors R7, R8, and R10 are pull downresistors to keep transistors Q20, and Q22 off, and Q21 on foractivating the low impedance clamp. The diodes D11 and D12 protect thebase to emitter junctions of transistors Q20 and Q21, respectively.Diodes D11 and D12 also prevent the base to emitter junctions of thesetransistors from entering the zener conduction region when transistorQ20 is off but there is still a +Gate-bias voltage on the gate oftransistor Q13, and when transistor Q20 is on but transistor Q21 is off.

Because the bridge is symmetrical, the same operation applies to thetransistors Q2 and Q12. Specifically, a positive going pulse withrespect to ground-return applied to pin P2A turns on transistor Q12 viathe push-pull driver configuration of transistors Q14-Q17 and thetransformer T2.

A positive going pulse on pins P4A and P4B turns on transistor Q2 byturning on transistor Q9 and turning off transistor Q10, respectively.Pin P4C is held at ground potential to keep Q2 turned on. A pulse on pinP4B turns on transistor Q10 and thus provides a low impedance clamp tothe gate of transistor Q2, turning Q2 off. Diodes D9 and D10 function inthe same way as diodes D11 and D12.

In the event that the defibrillation pulse should not be delivered tothe heart, pin P5A is set high to direct the pulse to an external load(not shown).

The circuit 10 is used in an implantable defibrillator unit 14 as partof an implantable defibrillation system illustrated in FIG. 2.Typically, the defibrillator unit 14 also includes an arrhythmiadetection circuit 16 and a stimulation control circuit 18 connected toboth the detection circuit 16 and the output circuit 10. Defibrillatorunit 14, including the circuits 10, 16, and 18, is of a size whereby itcomfortably can be implanted in the abdomen of the patient.

The arrhythmia detection circuit 1 is connected to sensing electrodes 20implanted in or on the heart. The output circuit 10 is connected toimplanted electrodes 22 and 24, shown mounted on the heart forperforming defibrillation. The control circuit 18 is triggered by thearrhythmia detection circuit 16 to trigger the output circuit 10 andapply a defibrillation pulse to the heart across electrodes 22 and 24.The output circuit 10 is capable of delivering mono-phasic, bi-phasic,tri-phasic, . . . n-phasic, and sequential defibrillation pulses to theheart depending upon the control signals applied to the input signalpins P1A-P5A, P3B, P4B, P3C and P4C. The desired type of defibrillationpulse delivered to the heart is programmed in the control circuit 18which applies the necessary signals to the appropriate signal pins.

As mentioned previously, transistors Q1 and Q12 determine themulti-phasic nature of the defibrillation pulse, and transistors Q2 andQ13 determine the polarity of the pulse. Transistors Q1 and Q13 are usedtogether to generate positive pulses. Transistors Q2 and Q12 are usedtogether to generate negative pulses. With transistor Q!3 turned on,positive pulses will be generated, the duration of which is determinedby the length of time transistor Q1 is turned on. The same is true fornegative pulses generated by maintaining transistor Q2 on, and varyingthe pulse duration by the duration which transistor Q12 is on. Togenerate multi-phasic pulses, the activation of transistors Q1 and Q13is followed by the activation of transistors Q2 and Q12, or vice versa,for as many phases of the pulse desired. The actual pulse, whetherpositive or negative, exponentially decreases in magnitude as itnormally would, across capacitor C3.

With reference to FIGS. 1 and 3a-3h, representative defibrillationpulses which can be delivered to the heart by the output circuit 10 willnow be described.

FIG. 3a illustrates a mono-phasic pulse with positive polarity. Toachieve this pulse, input signal pins P3A and P3B are set high and inputsignal pin P3C is grounded to turn transistor Q13 on. A positive goingpulse of a predetermined duration is then obtained by setting pin P1Ahigh to turn on transistor Q1.

FIG. 3b illustrates a mono-phasic pulse with negative polarity. This isachieved by setting pins P4A and P4B high and setting pin P4C low toturn on transistor Q2. A pulse is then applied to pin P2A to turn ontransistor Q12.

FIG. 3c illustrates a bi-phasic pulse with positive polarity achieved bysetting pin P3A and pin P3B high and setting pin P3C low. A pulse isapplied to pin P1A, turning transistor Q1 on. Thereafter, pin P4A andpin P4B are set high and pin P4C is set low to turn on transistor Q2. Apulse is then applied to pin P2A to turn on transistor Q12.

FIG. 3d illustrates a bi-phasic pulse with negative polarity achieved bysetting pin P4A and pin P4B high and setting pin P4C low. This turns ontransistor Q2. A pulse is then applied to pin P2A, turning on transistorQ12. This creates the negative portion of the bi-phasic pulse.Thereafter, pins P3A and P3B are set high and pin P3C is set low, and apulse is applied to pin P!A. This turns on transistors Q13 and Q1 tocreate the positive portion of the bi-phasic pulse.

FIG. 3e illustrates sequential pulses with positive polarity. This isachieved by setting pin P3A and pin P3B high and setting pin P3C low toturn on transistor Q13. A pulse is then applied to pin P1A, turningtransistor Q1 on, and repeated for as many positive pulses needed.

FIG. 3f illustrates sequential pulses with negative polarity beingachieved by setting pins P4A and P4B high and setting pin P4C low toturn on transistor Q2. Repeated pulses are applied to pin P2A to turn ontransistor Q12 for as many negative pulses desired. As seen in FIGS. 3eand 3f, no voltage is lost across capacitor C3.

FIG. 3g illustrates a tri-phasic pulse with positive polarity. This isachieved by first setting pin P3A and pin P3B high and setting pin P3Clow. A pulse is then applied to pin P1A. Then, pins P4A and P4B are sethigh and pin P4C set low. A pulse is then applied to pin P2A. Finally,pins P3A and P3B are set high and pin P3C is set low. A pulse is appliedto pin P1A.

FIG. 3h illustrates a tri-phasic pulse with negative polarity. This isachieved by first setting pins P4A and P4B high and setting pin P4C low.A pulse is applied to pin P2A. Then, pins P3A and P3B are set high andpin P3C is set low. A pulse is applied to pin P1A. Finally, pins P4A andP4B are set high and pin P4C is set low. A pulse is then applied to pinP2A.

Energy flow is always from Vcap, through transistor Q1, out throughpatch+, through the heart, into patch-, through transistor Q13, toground-return, or from Vcap, through transistor Q12, out through patch-,through the heart, into path+, through transistor Q2, and toground-return.

The advantages of this output bridge circuit are the independent on/offcontrols of transistors Q1, Q2, Q12, and Q13. The three control pinsP4A, P4B, P4C, and P3A, P3B, and P3C for the gate drive circuits oftransistors Q2 and Q13, respectively, allow separate control to turn onand off, and reduce current variations with respect to time. Inoperation, at least one of the two patch leads path+or patch-is alwaysconnected to ground-return. Furthermore, a n-phasic defibrillation pulsecan easily be generated by alternating the activation of transistors Q1and Q13 together, with the activation of transistors Q2 and Q12together.

The above description is intended by way of example only and is notintended to limit the present invention in any way except as set forthin the following claims.

We claim:
 1. An output circuit for use in an implantable defibrillationsystem, said circuit comprising:capacitor means for storing apredetermined voltage; first and second switching means, both connectedto said capacitor means and capable of being triggered to activeconditions; a ground-return terminal; first and second electrode leadterminals connected to said first and second switching means,respectively; .[.third and.]. fourth .Iadd.and third .Iaddend.switchingmeans connected to said first and second lead terminals, respectively,for selectively connecting said first and second electrode leadterminals, respectively, to said ground-return terminal when triggeredto active conditions; and triggering means for triggering said first andsaid third switching means to said active conditions to allow voltagestored by said capacitor means to discharge through said first andsecond electrode lead terminals in a first polarity, and for triggeringsaid second and fourth switching means to said active conditions toallow voltage stored by said capacitor means to discharge through saidfirst and second electrode lead terminals in a second polarity oppositeto said first polarity.
 2. The circuit of claim 1, and furthercomprising first and second push-pull driver circuits; first and secondcontrol pins connected to said first and second push-pull drivercircuits, respectively; and first and second pulse transformers; saidfirst and second pulse transformers including primary and secondarywindings, said secondary windings being connected to said first andsecond switching means, said primary windings being connected to saidpush-pull driver circuits, and said first and second switching meansbeing triggered to said active conditions by applying an electricalpulse to said first and second control pins.
 3. An implantabledefibrillation system for delivering mono-phasic, multi-phasic, andsequential defibrillation pulses to a heart via a pair of electrodesimplanted on or about the heart, said system comprising:an outputcircuit comprising capacitor means for storing a predetermined voltage,first and second switching means both connected to said capacitor meansand capable of being triggered to active conditions; a ground returnterminal; first and second electrode lead terminals connected,respectively to said first and second switching means and to said pairof electrodes; .[.third and.]. fourth .Iadd.and third .Iaddend.switchingmeans for selectively connecting said first and second electrode leadterminals, respectively, to said ground return terminal when triggeredto active conditions; a control circuit for selectively triggering saidfirst and said third switching means to said active conditions forallowing voltage stored by said capacitor means to discharge throughsaid first and second electrode lead terminals in a first polarity, andtriggering said second and fourth switching means to said activeconditions for allowing voltage stored by said capacitor means todischarge through said first and second electrode lead terminals in asecond polarity opposite to said first polarity.
 4. A method forgenerating a multi-phasic defibrillation pulse via four independentlycontrolled electrical switching elements for delivery to the heart of apatient via first and second electrodes implanted on or about the heart,said method comprising the steps of:charging a capacitor to apredetermined voltage; triggering a first electrical switching elementconnected to said capacitor and said first electrode to an activecondition and triggering a third electrical switching element connectedto said second electrode and a ground terminal to an active conditionfor delivering voltage through said first an second electrodes to theheart in a first polarity; triggering a second electrical switchingelement connected to said capacitor and said second electrode to anactive condition and triggering a fourth electrical switching elementconnected to said first electrode and a ground terminal to an activecondition for delivering voltage through said first and secondelectrodes to the heart in a second polarity opposite to said firstpolarity.
 5. An implantable defibrillation system for deliveringmono-phasic, multi-phasic and sequential defibrillation pulses to aheart via a pair of discharge electrodes implanted on or about theheart, said system comprising:sensing electrode means mounted on orabout the heart; arrhythmia sensing means connected to said sensingelectrode means for detecting an arrhythmia of the heart; an outputcircuit comprising capacitor means for storing a predetermined voltage;first and second switching means connected to said capacitor means andsaid discharge electrodes, and capable of being triggered to activeconditions; a ground return terminal.Iadd.; .Iaddend.first and secondelectrode lead terminals connected, respectively, to said first andsecond switching means and to said pair of electrodes; .[.third and.].fourth .Iadd.and third .Iaddend.switching means for selectivelyconnecting said first and second electrode lead terminals, respectively,to said ground return terminal when triggered to active conditions;control means for selectively triggering said first and said thirdswitching means to said active conditions for allowing voltage stored bysaid capacitor means to discharge through said first and secondelectrode lead terminals in a first polarity, and triggering said secondand fourth switching means to said active conditions for allowingvoltage stored by said capacitor means to discharge through said firstand second electrode lead terminals in a second polarity opposite tosaid first polarity.